1. Technical Field
The present invention relates to a semiconductor system, and more particularly, to a semiconductor system including a controller and a memory.
2. Related Art
A controller and a memory in a semiconductor system communicate with each other through a plurality of channels. The channels include a command channel for transmitting a command signal, a clock channel for transmitting a clock signal, a data channel for transmitting a data signal, and so forth. The controller transmits a clock signal to the memory and transmits a command signal and a data signal in synchronization with the clock signal. The memory receives the clock signal through the clock channel, and receives the command signal and the data through the command channel and the data channel, respectively, in synchronization with the clock signal. Accordingly, the controller and the memory can communicate with each other based on the clock signal.
FIG. 1 is an exemplary timing diagram showing clock signals transmitted from a controller to a memory through channels and internal clock signals generated within the memory. The controller transmits a first clock signal HCLK and a second clock signal WCLK to the memory. The second clock signal WCLK is a clock that may be used for data input/output operations, and the first clock HCLK is a clock signal that may be used for operations other than the data input/output operations. The memory receives the first and second clock signals HCLK and WCLK and generates first and second internal clock signals CLK0 and CLK90. The first and second clock signals CLK0 and CLK90 are generated, for example, to allow the memory to perform a double data rate (DDR) operation. The phase difference between the first and second clock signals CLK0 and CLK90 is 90°, and data can be inputted and outputted in synchronization with the rising edge and the falling edge of the second clock signal WCLK.
The controller generates and outputs the second clock signal WCLK, which has the same phase as the first clock signal HCLK and twice the frequency of the first clock signal HCLK, for high speed data communication with the memory. A clock generation unit is provided in the memory to receive the first and second clock signals HCLK and WCLK and to generate the first and second internal clock signals CLK0 and CLK90. The clock generation unit generates two clock signals, one signal with a 90° phase shift, because the memory does not operate internally with a clock at the same frequency of the second clock signal WCLK.
The memory provides feedback information to the controller regarding whether the first and second clock signals HCLK and WCLK have a corresponding phase. When the phases of the first and second clock signals HCLK and WCLK do not correspond to each other, a training operation is performed to correct the first and second clock signals HCLK and WCLK so that the first and second clock signals HCLK and WCLK correspond in phase. Therefore, the controller and the memory may have circuits that perform the training operation.
FIGS. 2a and 2b are timing diagrams respectively showing situations where first and second internal clock signals are normally generated and where the first and second internal clock signals are generated with erroneous timing, with respect to a power-down mode exit time. The memory may operate in a power-down mode to reduce power consumption, and data communication is not performed in the power-down mode. The memory operates in power-down mode when the power down signal PWRDN is at a high level. Accordingly, the memory may not receive the second clock signal WCLK in the power-down mode. When the memory no longer operates in the power-down mode, the memory may receive the first and second clock signals HCLK and WCLK and generate the first and second internal clock signals CLK0 and CLK90. Referring to FIG. 2A, the memory generates the first internal clock signal CLK0 at the rising edge of the second clock WCLK. When the power-down signal PWRDN changes to a low level (Power down mode exit) during a low level duration of the first clock signal HCLK, the first internal clock signal CLK0 may be normally generated at the rising edges of the first clock signal HCLK and the second clock signal WCLK.
Conversely, referring to FIG. 2B, when the power down exit happens during a high level duration of the first clock signal HCLK, the first internal clock signal CLK0 is generated at the falling edge of the first clock signal HCLK and the rising edge of the second clock signal WCLK. In this situation, the memory creates erroneous timing. In response to the erroneous timing, the controller may transmit a command to the memory to invert the phases of the first internal clock signal CLK0 and the second internal clock signal CLK90 to generate the first internal clock signal CLK0 at the rising edges of the first clock signal HCLK and the second clock signal WCLK.